The PC104/PANAVIA/T2/R2 PANAVIA serial data interface card is configured as a 16 bit Stack-through PC/104 interface card. It comprises of two independent transmitter channels that act as Bus Traffic Simulators and two independent receiver channels that provide advanced Real Time Monitor and Data Acquisition functions. The functions on all four channels are available concurrently at full performance level. The card also contains, a microprocessor and Dual Port memory for ease of interfacing to the PC/104 bus.
PANAVIA serial interface card
|PC/104/PANAVIA||PANAVIA 2Tx/2Rx card with 16-bit 'C' Drivers|
Two independent transmit and two
independent receive channels.
Continuous bit synchronization clock at 64Khz +/- 5% and 50% duty cycle (Tx).
Dynamic update of transmitted data in real time.
2kB Dual port RAM for holding received Tag data words or Tag transmit tables.
Ping-Pong double buffering of received data.
Transmission of sub-set of Tags, i.e.
Transmission of Tag 21 thru Tag 25 only, etc.
The constituent parts of the module comprise of line drivers for transmitting differential clock and
data to a PANAVIA databus, a proprietary FPGA transmitter circuit, a dual port RAM for interface
to the PC/104 bus and a Microcontroller executing the transmitter firmware.
All transmitted data is retrieved from the dual port RAM by the microprocessor and sent to the FPGA
circuit for transmission.
The data is transmitted as standard 32 bit data with the Tag, Control bits and data fields in their
correct positions as defined in the PANAVIA specification.
The Parity is generated and set to Odd as per the PANAVIA data standard.
The PC/104-PANAVIA/T2 executes autonomously instructions held in the interface memory.
For each simulated PANAVIA transmitter, all Tags can be generated or alternatively just a sub-set
group of Tags can be generated. Tag data descriptors can be updated during simulation at any time
without corrupting the transmission.
The constituent parts of the interface comprise of line receivers for accepting differential clock and data
from a PANAVIA databus, a proprietary FPGA receiver circuit, a dual port RAM for interface to the PC/104
local bus and a Microcontroller executing the receiver firmware. All received data is processed by the
microprocessor and stored in the dual port RAM according to the channel number and Tag value.
The data is stored in raw 26-bit form with the Tag, Control bits and data field left in their correct position as
defined in the PANAVIA specification. The Parity is not checked, but is relayed in its original state giving the
option to check and handle errors, etc. A channel Status register provides information about the state of the
PANAVIA clock for each interrogated channel.
This ensures that the data being retrieved is "live" data and not static left over from a previous bus activity
session. The firmware now supports double buffering of received data via a "ping-pong" method, a PC
interrupt can be enabled/disabled on a channel by channel basis, and a TAG0 counter for each channel is
provided. The PC interrupt when enabled is asserted when TAG0 has been received.
"C" Source Library
A "C" Source code driver library accompanies this product and this is available as either a 16-bit or
a 32-bit Microsoft Windows driver.